1. Technical Field
The invention relates generally to semiconductor memory fabrication, and more particularly, to a self-aligned strap for embedded trench memory, e.g., a trench capacitor, on a hybrid orientation technology (HOT) substrate and related method.
2. Background Art
As technologies become increasingly complex, demand for integrated circuits (IC) having more functionality is growing. In order to provide ICs with optimum designs, high-performance complementary metal-oxide semiconductor (CMOS) devices are required with additional features such as embedded memory devices like dynamic random access memory (DRAM). A challenge that arises relative to providing all of these features is that each feature is optimized under different conditions. For example, high-performance CMOS devices may be completed on silicon on insulator (SOI) wafers but memory devices may be built in bulk silicon.
Conventional techniques exist for making patterned SOI (part bulk and part SOI) wafers for the purposes of merging the best of “bulk technologies” with the best of “SOI technologies.” One such technique that utilizes this approach integrates DRAM in SOI. In this case, the DRAM array blocks are built in bulk silicon and logic is built in the SOI. The use of SOI and bulk silicon allows for different crystalline orientations on a surface of the substrate. This process technology is referred to as hybrid (surface) orientation technology (HOT).
One challenge relative to HOT technology and embedded memory is efficiently generating a low resistance strap to electrically couple a source/drain region of a transistor on the SOI substrate to an electrode of the embedded memory (e.g., trench capacitor) in the bulk silicon. In particular, conventional techniques require extra masks and cannot generate the strap in a self-aligned manner. Accordingly, the conventional techniques present a complex and costly approach.